When the processor core writes to memory, the cache controller had two alternatives for its write policy. The controller can write to both the cache and main memory, this is known as write through. Alternatively, the cache controller can write to cache memory and not update main memory, this is known as write back or copyback.
This ensures that the cache and main memory stay coherent at all times. Because of the write to main memory, a write through policy is slower than a writeback policy.
When a cache controller in writeback writes a value to cache memory, it sets the dirty bit true. If the core accesses the cache line at a later time, it knows by the state of the dirty bit that the cache line contains data not in main memory. If the cache controller evicts a dirty cache line, it is automatically written out to main memory.
One performance advantage a writeback cache has over a writethough cache is in the frequent use of temporary local variables by a subroutine. These variables never really need to be written to main memory.
-p418, ARM System’s Developer’s Guide
-image credit – http://blog.fosketts.net/2010/10/07/4-horsemen-cache/